post-ASML_era

• module.json — Agentic module schema role assignments

Module: docs/post-ASML_era Status: Active · Revision 1.0.0 Updated: 2026-08-08 Series: TriadicFrameworks Canonical Reference

This directory contains the foundational reference series for temporal manufacturing in the post-ASML era. The series defines — from physical theory through manufacturing infrastructure, metrology, design rules, and architectural methodology — the complete knowledge base for Substrate Clarity–based computing.

As of 08/15/2026, no one else in the mainstream semiconductor industry or academic literature is publishing under these exact terms, because "Temporal Manufacturing" and "Substrate Clarity" are new/open yet domain-specific nomenclatures currently unique to the TriadicFrameworks ontology.

When academic or corporate researchers write about the "post-ASML era", they are focusing on physical engineering alternatives to EUV (like the startup Substrate using particle accelerators, or Canon using Nanoimprint lithography). Our framework, however, shifts the paradigm from spatial mechanics to temporal address mapping.

While the industry uses different words, there are significant parallel research tracks that align perfectly with the "seeds" we are trying to plant. Here is how our concepts map to active external research where others might find our examples highly valuable:

💡 Framework Overlaps & Industry Parallels#

1. Substrate Clarity (SC) vs. Dephasing & Coherence Times#

In mainstream physics, what TriadicFrameworks describes as "Substrate Clarity"—the capacity of a substrate to hold distinct temporal addresses without "temporal smearing"—is heavily researched in Quantum Computing and Spintronics as Phase Coherence Time ($T_2$) and Inhomogeneous Dephasing ($T_2^*$).

• Who is publishing: Centers like the Chicago Quantum Exchange and corporate labs (IBM, Intel) publish extensively on "substrate engineering"—specifically using isotopically pure silicon-28 or diamond substrates to eliminate spatial/thermal defects that cause "smearing" of quantum/temporal states.
• The Seed Alignment: Our classification of SC-I through SC-III provides an architectural abstraction layer that these material scientists currently lack.

2. Temporal Manufacturing vs. Polymorphic & Magnonic Computing#

Our X post describes shifting from features per mm² to "operations per coherence cycle" using a temporal address space. The closest industry equivalents are Magnonic (Spin-Wave) Computing and Time-Domain Polymorphic Circuits.

• Who is publishing: Academic groups at TU Kaiserslautern and IMEC are researching circuits where data is encoded not by a physical wire's voltage, but by the phase and time-of-arrival of a spin wave passing through a shared magnetic substrate.
• The Seed Alignment: These researchers struggle with "temporal design rules". Our proposed Temporal Design Rule Check (TDRC) and Causal Graph Verification (CGV) are exactly the types of EDA abstractions they need to scale past simple laboratory gates.

3. Fab Reorganization (SCR) vs. Elastic Timed Circuits#

We propose a fab organized around a Substrate Coherence Regime (SCR) zone sharing a coherence clock rather than physical stepper clusters.

• Who is publishing: The asynchronous and "clockless" computing communities (such as researchers working on Asynchronous Wave Pipelines or Elastic Timed Circuits) write extensively on handling data handoffs via localized latency tolerances rather than global clock networks.
• The Seed Alignment: While you view this purely as a digital design challenge, our framework ties it directly to the foundational physics of the manufacturing floor, which is a completely novel way to frame the problem.

📊 System Mapping: Triadic vs. Academic Lit#

➡️ How to Seed These Ideas#

Because our work is designed to be an open educational resource, using standard industry crosswalks will help others find it. We want these examples to catch the eyes of traditional engineers, we are targeting:

1. The Asynchronous Logic Community: They already think in terms of causal graphs rather than spatial clock ticks.
2. Next-Gen EDA Pioneers: Open-source EDA movements (like OpenROAD) are actively looking for alternative architectural models to bypass traditional silicon limitations.

To map our seeds further, we ask AI what specific physical mechanisms (e.g., spin waves, optical lattices, or molecular states) do you envision the Temporal Commit Units (TCUs) interacting with to lock an operation into the substrate?

Document Catalog#

Note on TCT_Protocol.md path. Prior documents in this series reference the TCT Protocol at docs/metrology/TCT_Protocol.md. That path is maintained as a redirect stub resolving here. The canonical location is docs/post-ASML_era/TCT_Protocol.md.

Note on The_TRS-Aware_PDK_Specification.md. Referenced elsewhere as docs/eda/PostASML_PDK_Integration.md. That path resolves here via redirect stub.

Dependency Graph#

Documents must be read — and authored revisions must be evaluated — in dependency order. An arrow (→) indicates "depends on" or "assumes familiarity with."

The_Multi-Regime_Semiconductor_Model.md   [Physical foundation — INFORMATIVE]
        │
        ▼
TCT_Protocol.md ──────────────────────────────────────┐
        │                                              │
        ▼                                              │
The_TGI_Metrology_Standard.md                         │
        │                                              │
        ▼                                              │
The_Temporal_Manufacturing_Primer.md  ◄───────────────┘
        │
        ├──────────────────────┐
        ▼                      ▼
The_SCR_Specification.md   The_TRS-Aware_PDK_Specification.md
        │                          │
        └──────────┬───────────────┘
                   ▼
        The_Logic_Folding_Architecture_Guide.md

For normative rule resolution, the dependency graph also determines precedence: a downstream document's normative requirements take precedence over any conflicting guidance in an upstream document.

Reading Paths by Audience#

Fab Architect / Equipment Vendor#

1. The_Temporal_Manufacturing_Primer.md
2. The_SCR_Specification.md ← primary reference
3. The_TGI_Metrology_Standard.md (§4–§6)
4. The_TRS-Aware_PDK_Specification.md (§6 Coherence Budget Tables)

Process Engineer / Metrology#

1. The_Multi-Regime_Semiconductor_Model.md ← start here for physical grounding
2. TCT_Protocol.md ← primary reference
3. The_TGI_Metrology_Standard.md ← primary reference
4. The_Temporal_Manufacturing_Primer.md (§3 Substrate Clarity)

EDA Tool Developer / PDK Integrator#

1. The_Temporal_Manufacturing_Primer.md
2. The_TRS-Aware_PDK_Specification.md ← primary reference
3. The_SCR_Specification.md (§11 SCR Interface Contracts)
4. The_TGI_Metrology_Standard.md (§9 RWDL and SC_eff)

Logic Architect / RTL Designer#

1. The_Temporal_Manufacturing_Primer.md
2. The_Logic_Folding_Architecture_Guide.md ← primary reference
3. The_TRS-Aware_PDK_Specification.md (§5 Temporal Design Rules, §7 TTF Arc Library)

Materials Engineer / Process Developer#

1. The_Multi-Regime_Semiconductor_Model.md ← primary reference
2. TCT_Protocol.md
3. The_TGI_Metrology_Standard.md (§6 Interface Continuity, §9 CLG)

Timing Engineer#

1. The_TRS-Aware_PDK_Specification.md (§7 TTF Arc Library)
2. The_Logic_Folding_Architecture_Guide.md (§10 Timing Closure)
3. The_SCR_Specification.md (§6 SLF, §7 Inter-Zone Handoff)

Outbound Stub Registry#

The following files are referenced by documents in this module but have not yet been authored. They are scaffolded at the listed paths. Priority tiers:

• P1 — Referenced by ≥ 4 documents in this series; blocks process qualification
• P2 — Referenced by 2–3 documents; blocks EDA or design workflows
• P3 — Referenced by 1 document; extends the framework

Naming Conventions#

Authoring Notes#

• All documents in this series use MUST / MUST NOT / SHOULD / SHOULD NOT / MAY normative language as defined in each document's §1 Normative Language table.
• The MRSM (The_Multi-Regime_Semiconductor_Model.md) is INFORMATIVE. It does not impose normative requirements. Revisions that change model formula results by more than 5% at an SC class boundary require a cross-impact analysis across all dependent normative documents before merge.
• Revisions to SC class threshold values (0.92 and 0.75) require simultaneous updates to: TCT_Protocol.md §10, SC_Classification.md, The_TRS-Aware_PDK_Specification.md §13.2, and The_Multi-Regime_Semiconductor_Model.md §8.2.
• pae_Capture.md is the internal module capture index. It is maintained separately and does not follow the standard document template.