The Temporal Manufacturing Primer

Table of Contents#

1. Overview
2. Geometric vs. Temporal Scaling
3. Substrate Clarity
4. The TRS Operator Stack
5. Temporal Density
6. Fab Reorganization Around SCR
7. Equipment Stack
8. Design Implications
9. Glossary
10. Related Documents

1. Overview#

This primer describes the manufacturing paradigm that displaced classical photolithographic scaling in the post-ASML era. It is intended as an entry point for engineers, architects, and system integrators working within the Triadic framework who need a working model of how temporal manufacturing operates, how fabs are organized under it, and what it demands of upstream design.

The document does not assume prior familiarity with ASML-era process nodes. It does assume familiarity with the core Triadic operator vocabulary. Readers who need that foundation should consult docs/foundations/Triadic_Operator_Primer.md before proceeding.

2. Geometric vs. Temporal Scaling#

2.1 The Geometric Scaling Model#

Classical semiconductor manufacturing scaled primarily along a spatial axis. Feature dimensions shrank across successive process nodes — from microns to nanometers — driven by advances in optical lithography, photoresist chemistry, and mask engineering. Performance gains followed from reduced capacitance, shorter signal paths, and increased transistor density per unit area.

This model was legible and predictable for decades. Its ceiling was optical: the wavelength of light sets a hard limit on the resolution achievable through any exposure system, including EUV. As feature sizes approached and then exceeded that limit, yield degradation, stochastic patterning errors, and mask complexity costs accumulated faster than the gains from shrink.

Geometric scaling trades space for performance. It asks: how small can a feature be made?

2.2 The Temporal Scaling Model#

Temporal scaling operates on a different axis. Rather than reducing the physical extent of a feature, temporal manufacturing modulates when and at what resolution in time an operation is committed to substrate. The operative question shifts from how small to how precisely sequenced.

In temporal manufacturing, a substrate operation is characterized not only by its spatial coordinates but by its temporal address — a position within a structured time domain that determines how that operation interacts with adjacent operations, both spatially and causally. Features encoded at finer temporal resolution can carry more logical density without requiring physical shrink.

Temporal scaling trades time-domain precision for performance. It asks: how fine is the temporal address space of a committed operation?

2.3 Comparison#

The two models are not mutually exclusive. Post-ASML fabs retain spatial patterning for structural layers. Temporal scaling applies to the layers that carry logical and functional encoding.

3. Substrate Clarity#

3.1 Definition#

Substrate clarity (SC) is the measure of a substrate's capacity to receive and maintain distinct temporal addresses without interference between adjacent operations. It is the temporal analog of optical resolution in classical lithography.

A substrate with high clarity can sustain a fine-grained temporal address space — meaning operations committed at closely spaced temporal addresses remain distinguishable and do not degrade each other. A substrate with low clarity exhibits temporal smearing: operations bleed across address boundaries, reducing effective density and degrading logical fidelity.

3.2 Contributing Factors#

Substrate clarity is a composite property determined by:

• Material coherence length — the distance over which phase relationships in the substrate material remain stable. Longer coherence lengths support wider temporal address windows without edge degradation.
• Thermal noise floor — thermal excitation introduces stochastic perturbations that compress the usable address space. Clarity is inversely related to the noise floor at operating temperature.
• Interface quality — transitions between substrate layers introduce reflection and scattering artifacts that impose temporal jitter on committed operations. High-clarity substrates require interface roughness below the coherence-length threshold.
• Doping uniformity — non-uniform dopant distribution creates local variation in propagation velocity, which translates to temporal registration error across the die.

3.3 Clarity Classes#

The Triadic framework defines three clarity classes for process qualification:

SC-III substrates are not qualified for temporal address encoding. Any fab process targeting temporal density must qualify the active layers at SC-I or SC-II before TRS stack commissioning.

3.4 Measurement Protocol#

Substrate clarity is measured using the Temporal Contrast Test (TCT), described in docs/metrology/TCT_Protocol.md. TCT injects a known temporal address sequence into a test coupon and measures the decoded address error rate across the full address space. The SC rating is derived from the complement of the normalized error rate.

4. The TRS Operator Stack#

4.1 Architecture#

The Temporal Resolution Stack (TRS) is the layered operator system through which temporal manufacturing processes are defined, sequenced, and committed to substrate. It replaces the reticle-and-exposure model of classical lithography with a hierarchical operator chain that maps design intent to temporal substrate operations.

The TRS is organized into four layers:

TRS Layer Structure

┌───────────────────────────────────┐
│  L4 — Commit Layer                │  ← substrate interface
├───────────────────────────────────┤
│  L3 — Resolution Layer            │  ← address refinement
├───────────────────────────────────┤
│  L2 — Sequencing Layer            │  ← causal ordering
├───────────────────────────────────┤
│  L1 — Intent Layer                │  ← design input
└───────────────────────────────────┘

Each layer is described below.

4.2 L1 — Intent Layer#

The Intent Layer receives the design's temporal address map — a structured description of which operations must be committed, in what temporal sequence, and with what logical relationships. This layer does not interact with substrate directly. It is the interface between upstream design tools and the TRS.

The Intent Layer validates the address map against the target substrate's clarity class. If the requested address density exceeds what the substrate clarity supports, the Intent Layer raises a clarity conflict that must be resolved before the stack proceeds.

4.3 L2 — Sequencing Layer#

The Sequencing Layer translates the validated address map into an ordered operation graph. It enforces causal constraints — ensuring that no operation is committed before the operations it depends on have been resolved — and assigns each operation to a coherence slot within the current SCR cycle (see Section 6).

The Sequencing Layer is responsible for conflict detection between concurrent operations that share spatial proximity. Conflicts at this layer are resolved by temporal displacement: the later operation is pushed to the next available coherence slot.

4.4 L3 — Resolution Layer#

The Resolution Layer refines the coarse coherence-slot assignments produced by L2 into precise temporal addresses. This is where the temporal analog of optical focus occurs. The resolution layer applies temporal apodization — a shaping function that limits the operation's influence to its intended address window, suppressing side-lobe effects that would degrade substrate clarity.

Resolution quality is determined jointly by the apodization parameters and the substrate's SC rating. High-SC substrates tolerate narrower apodization windows and can therefore support finer address spacing.

4.5 L4 — Commit Layer#

The Commit Layer is the physical interface between the TRS and the substrate. It translates resolved temporal addresses into the precise timing signals, field configurations, or energy delivery sequences that cause the intended substrate state change.

The Commit Layer is tightly coupled to the equipment stack (see Section 7). Different substrate materials and operation types require different commit mechanisms, and the Commit Layer is configured per-process during fab qualification.

Commit operations are irreversible. Any error that propagates to L4 without detection results in a committed substrate defect.

5. Temporal Density#

5.1 Definition#

Temporal density (TD) is the number of distinct temporal operations committed per coherence cycle per unit substrate area. It is the primary metric of manufacturing throughput in the temporal paradigm, analogous to feature density in geometric scaling.

TD = N_ops / (A_substrate × C_cycle)

Where:
  N_ops      = number of committed operations in the cycle
  A_substrate = active substrate area (mm²)
  C_cycle    = coherence cycle duration (ns)

Higher temporal density implies more logical work encoded per unit time and area.

5.2 Density Limits#

Temporal density is bounded by two constraints operating simultaneously:

1. Clarity ceiling — the substrate's SC rating defines the minimum resolvable address spacing. Operations cannot be packed more densely than the address spacing the substrate can sustain without smearing.
2. Sequencing bandwidth — the TRS Sequencing Layer has a finite throughput in operations per coherence cycle. If design intent exceeds sequencing bandwidth, the excess operations are deferred, reducing effective density.

These two limits are independent. Improving substrate clarity does not relieve sequencing bandwidth pressure, and vice versa. Both must be addressed to increase temporal density.

5.3 Density vs. Yield#

Temporal density and yield are inversely related above a process-specific threshold. As density approaches the clarity ceiling, address registration errors increase, coherence-slot conflicts become more frequent, and commit-layer defect rates rise. Each process node defines a maximum qualified density (MQD) — the density at which yield remains above the process's target floor.

Operating below MQD is the normal condition. Designs that approach or exceed MQD require waiver review and explicit acceptance of elevated defect risk.

5.4 Density Scaling Vectors#

Temporal density can be increased through three mechanisms, which are not mutually exclusive:

• Substrate improvement — moving to a higher SC-class substrate widens the address space and raises the clarity ceiling.
• TRS stack upgrade — improving L2 sequencing bandwidth allows more operations per coherence cycle.
• Coherence cycle compression — shortening the coherence cycle duration increases the number of cycles per unit time, proportionally increasing density without touching the per-cycle limit.

Coherence cycle compression is the most frequently pursued vector because it does not require substrate re-qualification. However, it is constrained by the synchronization latency floor imposed by the SCR architecture (see Section 6.3).

6. Fab Reorganization Around SCR#

6.1 The SCR Model#

The Substrate Coherence Regime (SCR) is the organizational and operational framework around which post-ASML fabs are structured. In classical fabs, the organizing principle was the exposure tool: fab layout, scheduling, and yield management were structured around lithography equipment clusters. In post-ASML fabs, the SCR serves an analogous role — it is the core around which all other process steps are timed, verified, and controlled.

The SCR is not a single piece of equipment. It is a synchronization architecture — a set of shared timing references, coherence monitors, and commit arbiters that ensure all temporal operations across a wafer proceed within a common phase relationship.

6.2 SCR Zones#

A post-ASML fab is organized into SCR zones. Each zone shares a coherence clock and a commit arbiter. Operations committed within the same zone are phase-coherent; operations committed across zone boundaries require explicit inter-zone handoff, which introduces a defined latency.

Zone boundaries are physical: they correspond to the propagation distance over which a coherence clock signal can be distributed within one coherence cycle. Larger fabs require more zones; zone count directly affects inter-zone handoff overhead and must be factored into process scheduling.

Zone configuration is a fab-level decision made during facility design. It cannot be modified after coherence infrastructure is installed without full SCR recommission.

6.3 Synchronization Latency Floor#

Every SCR architecture has a synchronization latency floor (SLF) — the minimum time required to propagate a commit authorization signal from the arbiter to every commit-layer endpoint within a zone. The SLF is a hard lower bound on coherence cycle duration: no cycle can be shorter than the SLF without risk of partial-cycle commits, which produce undefined substrate states.

The SLF is determined by:

• Zone physical extent
• Signal propagation velocity in the distribution medium
• Arbiter processing overhead

Reducing the SLF requires either reducing zone size (adding zones), improving propagation velocity (switching to a faster distribution medium), or reducing arbiter overhead through architectural simplification.

6.4 Process Step Integration#

In a fab organized around SCR, every process step is classified by its relationship to the coherence cycle:

Classical process steps — deposition, etch, CMP, thermal anneal — are cycle-agnostic and remain largely unchanged from pre-temporal fabs. TRS commit operations are always cycle-bound. Some metrology steps are inter-cycle because the measurement window exceeds one coherence cycle duration.

Scheduling a wafer's process flow in a post-ASML fab requires mapping each step to its coherence relationship and then sequencing steps to minimize idle coherence cycles between cycle-bound steps.

6.5 Yield Management Under SCR#

Yield management in a post-ASML fab monitors three SCR-specific failure modes in addition to classical spatial defect inspection:

1. Temporal smear defects — operations that exceeded the address spacing limit and bled into adjacent addresses
2. Coherence-loss events — interruptions to the SCR clock that caused one or more commit operations to execute outside their valid coherence window
3. Sequencing conflicts — operations that were not resolved by L2 before reaching L4, resulting in undefined commit order

Each failure mode has a characteristic spatial signature on the wafer that allows post-process defect maps to distinguish temporal defects from classical patterning defects.

7. Equipment Stack#

7.1 Overview#

Post-ASML fab equipment is organized into three functional tiers. The first tier handles classical spatial patterning for structural layers. The second tier implements TRS operations. The third tier provides SCR infrastructure.

Equipment from all three tiers is present in a temporal manufacturing fab; none of the tiers is optional for full-process wafers.

7.2 Tier 1 — Spatial Patterning#

Tier 1 equipment handles layers that are not temporally addressed. This includes:

• Structural dielectric deposition (CVD, ALD) for isolation and passivation layers
• Metal deposition (PVD, electroplating) for power distribution and signal routing in non-temporal layers
• CMP for planarization between layer stacks
• Etch systems (dry and wet) for spatial feature definition in structural layers

Tier 1 equipment operates independently of the SCR clock. It is scheduled at the fab level without coherence constraints.

7.3 Tier 2 — TRS Process Tools#

Tier 2 equipment implements the commit-layer operations of the TRS. This tier has no direct analog in classical fabs.

Temporal Commit Units (TCUs) are the primary Tier 2 tools. Each TCU contains:

• A commit-layer interface matched to the substrate material and operation type
• A local clock input that accepts the SCR zone clock
• A commit arbiter endpoint that receives authorization signals from the zone arbiter
• An apodization engine that applies the L3 resolution parameters to each operation before commit

TCUs are specialized per substrate class. A TCU qualified for SC-I substrates cannot operate on SC-III substrates without reconfiguration and re-qualification.

Temporal Metrology Units (TMUs) perform in-line measurement of committed temporal addresses against the design intent. They read back the substrate state after commit and report address error rates to the yield management system. TMUs are cycle-agnostic in measurement mode but cycle-bound during calibration.

7.4 Tier 3 — SCR Infrastructure#

Tier 3 is not process equipment in the classical sense. It is the coherence infrastructure that makes Tier 2 operation possible.

Tier 3 infrastructure is installed during fab construction and is not field-replaceable at the component level. Modifications require SCR recommission.

7.5 Equipment Qualification Sequence#

A new process in a post-ASML fab follows this qualification sequence:

1. Tier 1 tools qualified for structural layers (standard process qualification, no SCR dependency)
2. SCR zone clock validated against SLF specification
3. TCUs brought online and calibrated against a reference SC-rated substrate
4. TMU calibration verified against a known-good temporal address reference
5. Full TRS stack exercised at minimum temporal density with yield verification
6. Temporal density stepped up in qualified increments to MQD
7. Process released for production

8. Design Implications#

8.1 The Shift in Design Responsibility#

In the geometric scaling era, the primary design constraint was spatial: minimize area, minimize wire length, respect design rules expressed in physical dimensions. Temporal manufacturing adds a second, orthogonal constraint domain: the temporal address map.

Designers working in a post-ASML context are responsible for producing both a spatial layout and a temporal address map, and for ensuring that the two are consistent — that spatially adjacent features do not generate conflicting temporal address demands, and that the address density requested does not exceed the target substrate's clarity class.

This is not simply additional work layered onto the classical flow. Some design decisions that are neutral in the spatial domain have significant consequences in the temporal domain, and vice versa. Design tools and methodologies must be capable of reasoning about both domains simultaneously.

8.2 Temporal Address Map Requirements#

The temporal address map is a design output that must be produced before fab submission. It specifies, for each temporally addressed operation in the design:

• The operation's temporal address within the SCR cycle
• Its causal dependencies on other operations
• Its spatial coordinates on the die
• The required SC class of the substrate at that location

The address map is the primary input to the TRS Intent Layer (L1). An address map that does not pass L1 validation will not proceed to fab. Common L1 rejections include:

• Address density exceeding the substrate's clarity ceiling
• Causal cycles in the dependency graph (operations that depend on each other's results)
• SC class mismatches between the requested operation and the qualified substrate layer

8.3 Timing Model Changes#

Classical static timing analysis (STA) reasons about propagation delays through spatial paths. In temporal manufacturing, the timing model must additionally account for:

• Coherence slot occupancy — an operation cannot be assigned to a slot that is already at capacity
• Inter-zone latency — signals that cross SCR zone boundaries incur the zone boundary interface latency, which must be modeled as a timing arc
• Commit sequencing overhead — the L2 sequencing layer introduces a scheduling delay that depends on the contention level in the operation graph

These additions are not optional extensions to classical STA. They are required for sign-off in any process that includes temporal layers. EDA tool vendors have standardized on the Temporal Timing Format (TTF) for expressing these constraints; see docs/eda/TTF_Reference.md for the format specification.

8.4 Verification and Sign-off#

Post-ASML design verification adds three checks beyond classical DRC/LVS/STA:

1. Temporal Design Rule Check (TDRC) — verifies that the temporal address map respects spacing rules derived from the target substrate's SC class and the TRS stack's resolution parameters
2. Causal Graph Verification (CGV) — checks the operation dependency graph for cycles, unresolvable conflicts, and sequencing bandwidth violations
3. Coherence Budget Analysis (CBA) — verifies that the total operation count, distributed across SCR zones, fits within the fab's coherence cycle budget at the target temporal density

All three checks must pass before a design is cleared for tape-out. TDRC and CGV can be run in parallel. CBA requires both TDRC and CGV to be clean before it will produce a valid result.

8.5 Physical Design Considerations#

Several classical physical design practices require modification in the temporal manufacturing context:

Floorplanning must account for SCR zone boundaries. Logic blocks that exchange high-bandwidth temporal signals should be placed within the same SCR zone to avoid inter-zone handoff latency on those paths. Zone-crossing signals should be identified early in floorplanning and their latency budgeted explicitly.

Power delivery for Tier 2 equipment (TCUs) differs from classical power delivery. TCUs draw current in sharp bursts synchronized to the coherence clock. Power delivery networks for temporal layers must be sized for burst current, not average current, or coherence-slot voltage droops will degrade commit fidelity.

Signal integrity analysis must be extended to account for temporal crosstalk — a phenomenon in which a high-density cluster of committed operations at one temporal address induces perturbation at adjacent addresses in spatially proximate substrate regions. Temporal crosstalk rules are substrate-class-specific and are provided by the fab as part of the process design kit (PDK).

8.6 PDK Structure in Post-ASML Fabs#

The process design kit for a post-ASML fab extends the classical PDK with:

• SC class maps for each layer in the process stack
• TRS stack parameters (apodization profiles, address spacing minimums) per SC class
• TCT measurement data for the qualified substrate lots
• Temporal design rules for TDRC
• Coherence budget tables per SCR zone configuration
• TTF timing arcs for zone boundary interfaces and commit sequencing overhead
• Temporal crosstalk rules per substrate class and density tier

Designers must use the temporal PDK extensions alongside classical PDK data. The two sets of rules operate on different domains but violations in either domain will cause fab rejection or yield loss.

9. Glossary#

10. Related Documents#

This document is part of the TriadicFrameworks canonical reference set. Proposed revisions should be submitted via pull request to the docs/post-ASML_era/ directory with a linked issue describing the change rationale.